This work deals extensively with the design and construction of an electronic dice display (EOD) with audio unit.  The device displays the of a ludo dice in numerical form and also produces sound as it displays the number.
The device works with principle of chance employee by ludo game players.  The output of the display is usually very rapid that the player does actually sex the number when the device is switched on so that it will purely be a game of chance.  When the off key is pressed, a patellar number is displayed and this number is the number, the player got.
The operation of the device starts by the generation of a pulse frequency.  The pulse frequency (square wave signal) generated by times (555 times) by connecting in an instable multibibrator.  The output from this timer is used in clocking the binary counter (mod to counter) but this counter is biased to count just from zero through six (0-6) as we have in a lodo game dice.  To achieve this bias in the mod 10 counter, the output from Qo, Q1 and Q2 were connected to the reset pins so that once the counter finishes the count of six or goes back to zero.
The result from the binary counter is then fed to the decoder driver before connecting it to seven segment so that the decoder will be able to covert the binary values to the decimal values that are being used in the ludo game dice.  The seven segment then displays the numbers by lighting the diodes that make up that particular value.
This device is being regulated by a latch (4-edge triggered flip-flop) which has two switches, one is used for putting the power supply and the other two push switches for the working of the dice display.

FIG 1.0    and gate diagram
Fig 1.1    capacitor diagram
Fig 1.2    seven segment diagram
Fig 3.01    block schematic diagram of an electronic dice display
Fig 3.02    block schematic diagram of an audio unit
Fig 3.03    555 timer schematic circuit diagram
Fig 3.04    555 timer block diagram
Fig 3.05    555 timer configuration
Fig 3.06    pin-out connection of a 555 timer
Fig 3.07a    555 timers in astable mode
Fig 3.07b    timing diagram
Fig 3.08    Jk flip flop symbol
Fig 3.09    delay flip-flop from Jk flip-flop
Fig 3.10a    delay flip-flop from JK flip-flop
Fig 3.10b    D flip-flop timing diagram
Fig 3.11    D type flip-flop in TTL
Fig 3.12    Quad-and gate symbol
Fig 3.13a    Circuit block diagram of a digital counter
Fig 3.13b    Output wave forms
Fig 3.14a    circuit block diagram of mod 10 counter
Fig 3.14b    output wave forms
Fig 3.15    Mod 6 counter using decade counter
Fig 3.16    functional logic diagram of BCD to decimal decoder
Fig 3.17    seven segment display layout arrangement
Fig 3.18    seven segment display connections
Fig 3.19    BCD to seven segment block diagram
Fig 3.20    7447 BCD to seven segment decoder driver functional
Fig 4.01    top view of 7414
Fig 4.02    counter configuration for the 7490A
Fig 4.03    top view of 7474
Fig 4.04    top view of SN 7447
Fig 4.05    top view of common unode display
Fig 5.01    output wave of 555 timers Table 3.1 time table for sK flip-flop
Table 3.2 delay flip-flop forms flip-flop
Table 3.4 and logic gate truth table
Table 3.5 table of counter output in various forms.
Table 3.7 bid to seven segment decoder truth table
Table 4.1a BCD count sequence
Table 5.0 procedure chart
Table 5.1 system flowchart
Table 6.0 program design
Table 6.1 program flowchart
 
Title page                                    ii
Approval page                            iii
Dedication                                  iv
Acknowledgement                      v
Abstract                                      vi
Organization of work                 viii
List of figures                             x
List of table                                xii
Table of content                         xiii

CHAPTER ONE
INTRODUCTION                                   1
1.0    Statement of problem                        1
1.1    purpose of study                                2
1.2    Aims and objectives                          2
1.3    Scope                                                 3
1.4    Limitations                                        3
1.5    Definitions of terms                          5

CHAPTER TWO
Literature Review                                      9

CHAPTER THREE
Description and Analysis of the Existing System            15
Organization structure                                                      16
Objectives of the existing system                                     17

CHAPTER FOUR
Design of the New System                        18
Output specification and design                20
Input specification and design                   29
File design                                                  38
Procedure chart                                          39
System flow chart                                      41
System requirement                                   42

CHAPTER FIVE    
Implementation                                          47
Program flowchart                                     49

CHAPTER SIX
Documentation                                           51

CHAPTER SEVEN
Recommendation and Conclusion             53        
7.1    Recommendation                              53
7.2    Conclusion                                        53
Reference                                                   55